3.1 Bare Metal Implementation

  1. Enabling Pattern Generation mode in the CTRLA register will override the TCE-generated waveform.
    WEX0.CTRLA = WEX_PGM_bm;
    Figure 3-1. CTRLA Register
  2. Every signal output must be enabled to be overridden in Pattern Generation mode. Every signal has a one-to-one relationship with the bits from the PGMOVR register.
    WEX0.PGMOVR  = WEX_PGMOVR0_bm | WEX_PGMOVR1_bm | WEX_PGMOVR2_bm | WEX_PGMOVR3_bm | 
                            WEX_PGMOVR4_bm | WEX_PGMOVR5_bm | WEX_PGMOVR6_bm | WEX_PGMOVR7_bm;
    Figure 3-2. Pattern Generation Override Register
  3. The PGMOUT register holds the pattern for every signal. It is worth mentioning that every signal has a one-to-one relationship with the bits from the PGMOUT register. For example, to achieve the pattern 0xAA, set bits 1, 3, 5, and 7 to high (‘1’) logic in the PGMOUT register:
    WEX0.PGMOUT = WEX_PGMOUT1_bm | WEX_PGMOUT3_bm | WEX_PGMOUT5_bm | WEX_PGMOUT7_bm;
    Figure 3-3. Pattern Generation Output Register
  4. After configuring the WEX in Pattern Generation mode, the user can toggle each signal state using the PGMOUT register.
    WEX0.PGMOUT = ~WEX0.PGMOUT;
  5. Add a delay to see when the toggling occurs.
    _delay_us(25);
  6. Port A pins 0-7 (PA0-7) are set as outputs by writing a ‘1’ to the corresponding bits in the Direction register of the port. These GPIOs are configured only to obtain a visible output.
    PORTA.DIRSET = PIN0_bm | PIN1_bm | PIN2_bm | PIN3_bm |
                            PIN4_bm | PIN5_bm | PIN6_bm | PIN7_bm;
  7. Make a setting in the PORTMUX to select the default PORT A pins.
    PORTMUX.TCEROUTEA = 0x0;
    Figure 3-4. WEX PORTMUX Register
  8. Enable the WEX’s outputs by setting the corresponding bits in the Output Override Enable register to enable the PORT A pins override.
    WEX0.OUTOVEN = WEX_OUTOVEN0_bm | WEX_OUTOVEN1_bm | WEX_OUTOVEN2_bm | WEX_OUTOVEN3_bm |
                            WEX_OUTOVEN4_bm | WEX_OUTOVEN5_bm | WEX_OUTOVEN6_bm | WEX_OUTOVEN7_bm;
    Figure 3-5. Output Override Enable Register
  9. The last step for this example is to enable the TCE module because the source clock that passes from TCE to WEX is needed to update the defined patterns.
    TCE0.CTRLA = TCE_ENABLE_bm;