25.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | Enable-protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKSEL[1:0] | CNTPRES[1:0] | SYNCPRES[1:0] | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:5 – CLKSEL[1:0] Clock Select
The Clock Select bit field selects the clock source of the TCD clock.
| Value | Name | Description |
|---|---|---|
0x0 | OSCHF | Internal High-Frequency Oscillator |
0x1 | PLL | PLL |
0x2 | EXTCLK | External Clock or external crystal oscillator |
0x3 | CLKPER | Main clock after prescaler (CLK_PER) |
Bits 4:3 – CNTPRES[1:0] Counter Prescaler
The Counter Prescaler bit field selects the division factor of the TCD counter clock.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV1 | Division factor 1 |
| 0x1 | DIV4 | Division factor 4 |
| 0x2 | DIV32 | Division factor 32 |
| 0x3 | - | Reserved |
Bits 2:1 – SYNCPRES[1:0] Synchronization Prescaler
The Synchronization Prescaler bit field selects the division factor of the TCD clock.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV1 | Division factor 1 |
| 0x1 | DIV2 | Division factor 2 |
| 0x2 | DIV4 | Division factor 4 |
| 0x3 | DIV8 | Division factor 8 |
Bit 0 – ENABLE Enable
When writing to this bit, it will automatically be synchronized to the TCD clock domain.
This bit can be changed as long as the synchronization of this bit is not ongoing. See the Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register.
This bit is not enable-protected.
| Value | Name | Description |
|---|---|---|
| 0 | NO | The TCD is disabled |
| 1 | YES | The TCD is enabled and running |