32.3 ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in the following figure. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). Refer to the following figure.
- Refer to the “I/O Ports” section in the “Electrical Specification” chapter.
Assumptions: Temperature = 50°C and external impedance pf 10 kΩ, 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2 μs + TC + [(Temperature - 25°C)(0.05 μs/°C)]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
- The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
- The charge holding capacitor (CHOLD) is not discharged after each conversion.
- The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification.