5.6.2 Linear Data Memory

The linear data memory is the region from FSR address 0x2000 to FSR address 0x2FEF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Refer to Figure 5-10 for the Linear Data Memory Map.

Important: The address range 0x2000 to 0x2FEF represents the complete addressable Linear Data Memory for PIC® devices (up to Bank 50). The actual implemented Linear Data Memory will differ from one device to the other in a family. Refer to the table below for the memory limits of PIC16(L)F18424/44 devices.

Table 5-4. General Purpose RAM Distribution
Bank #	{bank:offset}	Linear address	PIC16(L)F18424	PIC16(L)F18444
0	0x020-0x06F	0x2000-0x204F	80	80
1	0x0A0-0x0EF	0x2050-0x209F	80	80
2	0x120-0x16F	0x20A0-0x20EF	80	80
3	0x1A0-0x1EF	0x20F0-0x213F	80	80
4	0x220-0x26F	0x2140-0x218F	80	80
5	0x2A0-0x2EF	0x2190-0x21DF	80	80
6	0x320-0x32F	0x21E0-0x21EF	16	16

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.