6.7.1 Chip Erase

Erase the entire Flash (PFM and BFM memory regions) except the OTA BFM page using a DSU command.

When the device is protected, the debugger must reset the device to be detected. This ensures that internal registers are reset after the protected state is removed. The chip erase operation is triggered by writing a 1 to the Chip Erase bit in the Control register (DSUEXT.CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC).

The chip erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended that a chip erase be issued after a cold-plugging procedure to ensure that the device is in a known and safe state.

The recommended sequence is as follows:
  1. Perform the cold plugging procedure (refer to the Cold Plugging from DSU section in the PIC32CX-BZ3/PIC32CX-BZ36 and WBZ35x Module Family Data Sheet (DS70005541)). The device, then:
    1. Detects the debugger probe
    2. Holds the CPU in Reset
  2. Perform the chip erase command by writing a 1 to DSUEXT.CTRL.CE at (0x41000100 address). The device, then:
    1. Clears the system volatile memories
    2. Erases the whole Flash array (excluding OTP page)
    3. Erases the code protection row, removing the code protection security bit protection
  3. Check for completion by polling DSUEXT.STATUSA.DONE at (0x41000101 address) (read as 1 when completed).
  4. Reset the device.
Table 6-6. Reference
StepsCommands
Clear flags in STATUSAWriteD8(@DSUEXT.STATUSA.DSU_STATUSA_DONE_MASK)
Issue chip eraseWriteD8(@DSUEXT.CTRL, DSU_CTRL_CE)
Wait until erase is doneReadD8(@DSUEXT.STATUSA,StatusValue)

While ( (StatusValue& DSU_STATUSA_DONE) == 0) { ReadD8(@DSUEXT.STATUSA,StatusValue) }

Bit Fields Definitions
  • DSU_CTRL_CE = 0x10
  • DSU_STATUSA_MASK = 0x1F
  • DSU_STATUSA_DONE = 0x1
Note: The recommended time-out for waiting for erase completion is 20 seconds.