5.2 Revision 5

On this revision, the SPI clock net is improved to reduce any issues that might be caused by reflections. The SPI has been removed from the LCD (EXT4 connector) to reduce load on the clock net. The remaining clock lines have been divided into four terminated nets for each SPI source (EXT1, EXT2, EXT3, and EDBG) and routed in a star like layout. A series terminator resistor of 43ohm is placed on each clock net, close to the SPI clock pin. This reduces any issues that might be caused by reflections coming back from unterminated/unused clock lines. It also reduces the rise/fall time of the clock edges and that will also help to reduce any reflection issues.

Known issues

• There is no LC filter on the VDDPLL supply pin on the kit. This may cause excess ripple on the supply voltage which can cause the 48MHz PLL to not lock, which means USB applications may not work. For more information see the AT03463 SAM4S Schematic Checklist.