5.3 Revision 4

Known issues

• SAM4S has an on-die series termination of the SPI CLK which makes this signal not usable for a multi drop clock distribution because all devices along the line will see a fraction of VCC until the signal is reflected from the end of the transmission line. On the SAM4S Xplained Pro revision 4 this signal is routed to each extension connector with EXT1 at the end of the line. That means extensions that are connected along the transission line e.g. EXT3 header is likely to fail due to a non-monotinic edge caused by relections and the fraction of VCC that is present for a short time until the reflection comes back from the end of the line.

  Workaround:

  • By slowing down the clock rise time with a capacitor, and thus effectively increasing the line length at which point it becomes a transmission line, it is possible to remove the clock issue. A 56pF capacitor has been mounted on the bottom side of the board between the SPI clock and GND. This however reduces the maximum SPI clock speed and it is recommended to not run this faster than 30MHz (this also depends on how much additional capacitance is added by connected extensions and needs to be checked case by case). The capacitor was added on revision 4 on the bottom side of the EXT3 header.