2.6 Step 6: Implement Logic

Once the next-state logic and output logic are determined, the system can be implemented. For this implementation, the PIC18-Q24 MCU was chosen for its Signal Routing Port and CLC peripherals. The Signal Routing (SR) Port is a peripheral that allows flexible interconnection of other on-chip peripherals with optional clocked functionality. This allows the SR Port to act as a series of flip-flops with flexible input and clock options, serving as the memory element for the state machine. The CLCs are configurable logic cells that can be used to implement the output and next-state logic functions of the state machine. Refer to the PIC18-Q24 documentation for more details regarding the SR Port and CLC peripherals.

Each of the Boolean expressions that have been derived can be implemented using one of the eight CLCs present on the PIC18F56Q24. For each of the next-state logic expressions, the CLC can be configured in the “AND-OR” configuration. Because the first set of input gates in the “AND-OR” configuration are OR gates, the Boolean expressions need to be arranged to accommodate this. Any SOP expression can be written as a Product-of-Sums (POS) expression and vice versa, allowing the next-state logic expressions to be rearranged for implementation using one CLC each.

Equation 2-2. POS Expressions for Next-Stage Logic

X_{0} = {\bar{E}}_{} {\bar{X}}_{2} {\bar{X}}_{1} {\bar{X}}_{0} + {\bar{E}}_{} {\bar{X}}_{2} X_{1} {\bar{X}}_{0} = \bar{(E + X_{2} + X_{1} + X_{0)}} + \bar{(E + X_{2} + {\bar{X}}_{1} + X_{0})}

X_{1} = {\bar{E}}_{} {\bar{X}}_{2} {\bar{X}}_{1} {\bar{X}}_{0} + {\bar{E}}_{} {\bar{X}}_{2} X_{1} {\bar{X}}_{0} = \bar{(E + X_{2} + X_{1} + {\bar{X}}_{0})} + \bar{(E + X_{2} + {\bar{X}}_{1} + X_{0})}

X_{2} = E_{} {\bar{X}}_{2} + E_{} {\bar{X}}_{1} {\bar{X}}_{0} = \bar{(\bar{E} + X_{2})} + \bar{(\bar{E} + X_{1} + X_{0})}

To control the timing of the system, a PWM module is used. By using one of the MCU’s 16-bit PWM modules, it is possible to create a long delay followed by a short delay, ensuring that the ON times for the GO states are longer than the ON times for the SLOW states. The PWM is configured to have a frequency of 0.1Hz with a second pulse generated three seconds after the first pulse. These two signals can be labeled as $P_{L}$ for the long pulse and $P_{S}$ for the short pulse. A CLC is used to OR these two pulses together and is used as the clock source for the SR Port peripheral. This same CLC is also used to gate one of the pulses when the system is in the error state, ensuring that the timing is correctly synced when the error state is exited. The logic for this CLC can be written as follows:

Equation 2-3. Logic Expression for Clock Input

C L K = {\bar{X}}_{2} P_{L} + P_{S}

Tying it all together, the full logic implementation is shown below:

Figure 2-6. Traffic Light Logic Implementation