18.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 18-1. PPS Input Selection Table
PeripheralPPS Input RegisterRegister Reset Value at PORDefault Pin Selection at POR
14/16-Pin Devices20-Pin Devices14/16-Pin Devices20-Pin Devices
External Interrupt INTPPS‘b000 010RA2
Timer0 ClockT0CKIPPS‘b000 010RA2
Timer1 ClockT1CKIPPS‘b000 101RA5
Timer1 GateT1GPPS‘b000 100RA4
Timer3 ClockT3CKIPPS‘b010 101RC5
Timer3 GateT3GPPS‘b010 100RC4
Timer2 InputT2INPPS‘b000 101RA5
Timer4 InputT4INPPS‘b010 001RC1
Timer6 InputT6INPPS‘b010 010RC2
CCP1CCP1PPS‘b010 101RC5
CCP2CCP2PPS‘b010 011RC3
CWG1CWG1PPS‘b000 010RA2
CLCIN0CLCIN0PPS‘b010 011‘b000 010RC3RA2
CLCIN1CLCIN1PPS‘b010 100‘b010 011RC4RC3
CLCIN2CLCIN2PPS‘b010 001‘b001 100RC1RB4
CLCIN3CLCIN3PPS‘b000 101‘b001 101RA5RB5
SCL1/SCK1SSP1CLKPPS(1)‘b010 000‘b001 110RC0RB6
SDA1/SDI1SSP1DATPPS(1)‘b010 001‘b001 100RC1RB4
SS1SSP1SSPPS‘b010 011‘b010 110RC3RC6
SCL2/SCK2SSP2CLKPPS(1)‘b010 100‘b001 111RC4RB7
SDA2/SDI2SSP2DATPPS(1)‘b010 101‘b001 101RC5RB5
SS2SSP2SSPPS‘b000 000‘b000 001RA0RA1
RX1/DT1RX1PPS‘b010 101‘b001 101RC5RB5
CK1CK1PPS‘b010 100‘b001 111RC4RB7
RX2/DT2RX2PPS‘b010 001RC1
CK2CK2PPS‘b010 000RC0
ADC Conversion TriggerADACTPPS‘b010 010RC2
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.