PIC16F18026/46

Introduction
PIC16F180 Family Summary
Core Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F180 Microcontrollers
5 Register and Bit Naming Conventions
6 Register Legend
7 Enhanced Mid-Range CPU
8 Device Configuration
9 Memory Organization
10 Resets
11 OSC - Oscillator Module
12 INT - Interrupts
13 Sleep Mode
14 WDT - Watchdog Timer
15 NVM - Nonvolatile Memory Control
16 I/O Ports
17 IOC - Interrupt-on-Change
18 PPS - Peripheral Pin Select Module
19 TMR0 - Timer0 Module
20 TMR1 - Timer1 Module with Gate Control
21 TMR2 - Timer2 Module
22 NCO - Numerically Controlled Oscillator Module
23 CWG - Complementary Waveform Generator Module
24 CCP - Capture/Compare/PWM Module
25 Capture, Compare, and PWM Timers Selection
26 PWM - Pulse-Width Modulation
27 PWM Timers Selection
28 CLC - Configurable Logic Cell
- 28.1 CLC Setup
- 28.2 CLC Interrupts
- 28.3 Effects of a Reset
- 28.4 Output Mirror Copies
- 28.5 Operation During Sleep
- 28.6 CLC Setup Steps
- 28.7 Register Overlay
- 28.8 Register Definitions: Configurable Logic Cell
  - 28.8.1 CLCSELECT
    CLCSELECT
  - 28.8.2 CLCnCON
    CLCnCON
  - 28.8.3 CLCnPOL
    CLCnPOL
  - 28.8.4 CLCnSEL0
    CLCnSEL0
  - 28.8.5 CLCnSEL1
    CLCnSEL1
  - 28.8.6 CLCnSEL2
    CLCnSEL2
  - 28.8.7 CLCnSEL3
    CLCnSEL3
  - 28.8.8 CLCnGLS0
    CLCnGLS0
  - 28.8.9 CLCnGLS1
    CLCnGLS1
  - 28.8.10 CLCnGLS2
    CLCnGLS2
  - 28.8.11 CLCnGLS3
    CLCnGLS3
  - 28.8.12 CLCDATA
    CLCDATA
- 28.9 Register Summary - CLC Control
29 MSSP - Host Synchronous Serial Port Module
30 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
31 ADC - Analog-to-Digital Converter with Computation Module
32 DAC - Digital-to-Analog Converter Module
33 CMP - Comparator Module
34 FVR - Fixed Voltage Reference
35 Temperature Indicator Module
36 ZCD - Zero-Cross Detection Module
37 Charge Pump
38 Instruction Set Summary
39 ICSP™ - In-Circuit Serial Programming™
40 Register Summary
41 Electrical Specifications
42 DC and AC Characteristics Graphs and Tables
43 Packaging Information
44 Appendix A: Revision History
Microchip Information