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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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Product Pages
SAMA7G54
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8
Security and Cryptography Subsystem
8.4
Advanced Encryption Standard (AES)
8.4.4
Functional Description
8.4.4.11
Security Features
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
8.1
Overview
8.2
TrustZone Advanced Encryption Standard Bridge (TZAESB)
8.3
TrustZone AES Bridge Address Space Controller (TZAESBASC)
8.4
Advanced Encryption Standard (AES)
8.4.1
Description
8.4.2
Embedded Characteristics
8.4.3
Product Dependencies
8.4.4
Functional Description
8.4.4.1
AES Register Endianness
8.4.4.2
Operating Modes
8.4.4.3
Last Output Data Mode (CBC-MAC)
8.4.4.4
Galois/Counter Mode (GCM)
8.4.4.5
XEX-based Tweaked-codebook Mode (XTS)
8.4.4.6
Double Input Buffer
8.4.4.7
Temporary Secured Storage for Keys
8.4.4.8
Start Modes
8.4.4.9
Automatic Padding Mode
8.4.4.10
Secure Protocol Layers Improved Performances
8.4.4.11
Security Features
8.4.4.11.1
Private Key Bus
8.4.4.11.2
Unspecified Register Access Detection
8.4.4.11.3
Clearing Key on Tamper Event
8.4.4.11.4
Register Write Protection
8.4.4.11.5
Security and Safety Analysis and Reports
8.4.5
Register Summary
8.5
Secure Hash Algorithm (SHA)
8.6
Triple Data Encryption Standard (TDES)
8.7
Random Number Generator (TRNG)
8.8
Integrity Check Monitor (ICM)
8.9
Classical Public Key Cryptography Controller (CPKCC)
8.10
Security Module (SECUMOD)
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
8.4.4.11 Security Features
