7.2.7.5 I2SMCC Interrupt Enable Register A
This register can only be written if WPITEN is cleared in the Inter-IC Sound
Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this
register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | I2SMCC_IERA |
| Offset: | 0x10 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | RXROVF3 | RXLOVF3 | RXROVF2 | RXLOVF2 | RXROVF1 | RXLOVF1 | RXROVF0 | RXLOVF0 | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | RXRRDY3 | RXLRDY3 | RXRRDY2 | RXLRDY2 | RXRRDY1 | RXLRDY1 | RXRRDY0 | RXLRDY0 | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | TXRUNF3 | TXLUNF3 | TXRUNF2 | TXLUNF2 | TXRUNF1 | TXLUNF1 | TXRUNF0 | TXLUNF0 | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | TXRRDY3 | TXLRDY3 | TXRRDY2 | TXLRDY2 | TXRRDY1 | TXLRDY1 | TXRRDY0 | TXLRDY0 | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bits 25, 27, 29, 31 – RXROVFx
I2S Receive Right x or TDM Channel [2x]+1 Overrun Interrupt Enable
Bits 24, 26, 28, 30 – RXLOVFx
I2S Receive Left x or TDM Channel 2x Overrun Interrupt Enable
Bits 17, 19, 21, 23 – RXRRDYx
I2S Receive Right x or TDM Channel [2x]+1 Ready Interrupt Enable
Bits 16, 18, 20, 22 – RXLRDYx
I2S Receive Left x or TDM Channel 2x Ready Interrupt Enable
Bits 9, 11, 13, 15 – TXRUNFx
I2S Transmit Right x or TDM Channel [2x]+1 Underrun Interrupt Enable
Bits 8, 10, 12, 14 – TXLUNFx
I2S Transmit Left x or TDM Channel 2x Underrun Interrupt Enable
Bits 1, 3, 5, 7 – TXRRDYx
I2S Transmit Right x or TDM Channel [2x]+1 Ready Interrupt Enable
Bits 0, 2, 4, 6 – TXLRDYx
I2S Transmit Left x or TDM Channel 2x Ready Interrupt Enable
