Two Independent AES Cores with Independent Register Interfaces
Configurable AES Core Security Attribute
Compliant with FIPS Publication 197, Advanced Encryption Standard
(AES)
128-bit Cryptographic Key
10 Clock Cycles Encryption/Decryption Inherent Processing Time
Double Input Buffer Optimizes Runtime
Encryption Mode Based on CTR Mode
Abnormal Software Access Reports
Register Write Protection
Private Key Bus Access to the Private Key Internal Register Not Readable from any Peripheral or Software
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