Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Search
Product Pages
SAMA7G54
Home
7
Audio Subsystem
7.2
Inter-IC Sound Multi-Channel Controller (I2SMCC)
7.2.6
Functional Description
7.2.6.15
Functional Safety (Protection, Monitors and Reports)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
7.1
Overview
7.2
Inter-IC Sound Multi-Channel Controller (I2SMCC)
7.2.1
Description
7.2.2
Embedded Characteristics
7.2.3
Block Diagram
7.2.4
I/O Lines Description
7.2.5
Product Dependencies
7.2.6
Functional Description
7.2.6.1
Initialization
7.2.6.2
Basic Operation
7.2.6.3
Host, Controller and Client Modes
7.2.6.4
I
2
S Reception and Transmission Sequence
7.2.6.5
Left-Justified Reception and Transmission Sequence
7.2.6.6
TDM Reception and Transmission Sequence
7.2.6.7
Serial Clock and Word Select Generation
7.2.6.8
Mono
7.2.6.9
Wire Configurations
7.2.6.10
Holding Registers
7.2.6.11
DMA
Controller Operation
7.2.6.12
Loop-back Mode
7.2.6.13
Interrupts
7.2.6.14
Register Write Protection
7.2.6.15
Functional Safety (Protection, Monitors and Reports)
7.2.6.15.1
Protections
7.2.6.15.2
Monitors and Reports
7.2.7
Register Summary
7.3
Synchronous Serial Controller (SSC)
7.4
Sony/Philips Digital Interface Receiver (SPDIFRX)
7.5
Sony/Philips Digital Interface Transmitter (SPDIFTX)
7.6
Pulse Density Microphone Controller (PDMC)
7.7
Asynchronous Sample Rate Converter (ASRC)
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
7.2.6.15 Functional Safety (Protection, Monitors and Reports)
