Introduction

The AVR® DA MCU family of microcontrollers is equipped with a versatile type of timer/counter, which can be clocked by four of the frequency channels available to the user. The input frequency for the 12-bit Timer/Counter type D (TCD) varies from the 32.768 kHz input frequency provided by the Ultra Low-Power (ULP) internal or external oscillator, up to 48 MHz by using the Phase-Locked Loop (PLL) clock multiplication system. Thus, the TCD can be used to generate a wide range of Pulse-Width Modulation (PWM) signals.

The scope of this technical brief is to describe some of the TCD operating modes, emphasizing the TCD particularities and providing initialization code snippets. For a deeper understanding of the functionality, refer to the AVR DA data sheet.

This technical brief will describe two use cases where the AVR DA high-frequency sources are used as input clock for the TCD – the Internal High-Frequency Oscillator (OSCHF) and the PLL (clocked from the OSCHF):

• Generate Two PWM Signals in One Ramp Mode:

  The purpose of this example is to generate two PWM signals using the TCD configured in One Ramp mode and with OSCHF as input clock. OSCHF will be configured to run at 24 MHz and the PWM signals will be set as output to WOA on the PA4 pin and WOB on the PA5 pin. The PWM signal on WOA will have a 25% duty cycle and the signal on WOB will have a 30% duty cycle.

• Generate Two PWM Signals in Two Ramp Mode:

  The scope of this example is to generate two PWM signals using the TCD configured in Two Ramp mode with PLL as input clock. The PLL will be configured to run at 48 MHz and the PWM signals will be set as output to WOA on the PA4 pin and WOB on the PA5 pin. The PWM signal on WOA will have a 10% duty cycle and the signal on WOB will have a 20% duty cycle.