4 Generating Two PWM Signals in Two Ramp Mode

Use case description: The TCD will be initialized and configured to run in Two Ramp mode, to have the PLL as input clock running at 48 MHz, and to generate two PWM signals – WOA on the PA4 pin and WOB on the PA5 pin. The PWM signal on WOA will have a 10% duty cycle and the signal on WOB (PA5 pin) will have a 20% duty cycle.

Result: The TCD will generate one PWM signal with a 10% duty cycle on WOA (the PA4 pin) and one PWM signal with a 20% duty cycle on WOB.

In Two Ramp mode, the TCD counts up until it reaches the CMPACLR value, then it resets and counts up until it reaches the CMPBCLR value. Then, the TCD cycle is completed, and the counter restarts from 0x000.

T_{T C D_c y c l e = \frac{(C M P A C L R + 1 + C M P B C L R + 1)}{f_{C L K_T C D_C N T}}}

Configuring the Main Clock

To obtain the maximum input frequency for the TCD from the PLL, the OSCHF will be configured to run at the highest frequency (24 MHz). The maximum frequency achievable by the PLL is 48 MHz, so a multiplication factor of 2x will be used for the PLL.

Furthermore, the OSCHF will also serve as clock source for CLK_MAIN.

In the example code available in Appendix, the main clock initialization will be done in the CLK_Init() function.

Set OSCHF as clock source for the main clock. The following code snippet will switch the main clock to the OSCHF oscillator.
```
_PROTECTED_WRITE(CLKCTRL.MCLKCTRLA, CLKCTRL_CLKSEL_OSCHF_gc);
```
Wait for the clock switch process to complete. The following code snippet will demonstrate how to wait for the clock source switching process to finish.
```
while (CLKCTRL.MCLKSTATUS & CLKCTRL_SOSC_bm)
    {
        ;
    }
```
Set the OSCHF to run at 24 MHz. The following code snippet will set the OSCHF frequency to 24 MHz.
```
_PROTECTED_WRITE(CLKCTRL.OSCHFCTRLA, CLKCTRL_FREQSEL_24M_gc);
```
Configure the PLL settings – a multiplication factor of 2x will be chosen as the maximum PLL frequency is 48 MHz. The PLL system will not yet be active, but will start and generate when requested as a clock source by the TCD.
```
_PROTECTED_WRITE(CLKCTRL.PLLCTRLA, CLKCTRL_MULFAC_2x_gc);
```

Configuring PA4 and PA5 Pins as Output

The PA4 and PA5 pins must be configured as output pins for the WOA and WOB PWM signals. The following code snippet sets PA4 and PA5 pins as output low.

PORTA.DIRSET |= PIN4_bm | PIN5_bm;
PORTA.OUTSET |= PIN4_bm | PIN5_bm;

Note: In the example code available in Appendix, the pins initialization will be done in the PORT_Init() function.

Configuring the TCD Input Clock and Operation Mode

To Generate the two PWM signals using the TCD configured in One Ramp mode and with OSCHF as input clock, the following registers must be changed:

TCD0.CTRLA
TCD0.CTRLB
TCD0.CMPASET
TCD0.CMPACLR
TCD0.CMPBSET
TCD0.CMPBCLR

In the example code available in Appendix, the TCD initialization will be done in the TCD_Init() function.

Select the Waveform Generation Mode and configure the TCD.
Figure 4-2. TCD0.CTRLB Register Configuration

To use TCD0 in One Ramp mode, the WGMODE bit field in the TCD0.CTRLB register must be set to 0x0. The following code snippet configures TCD0 in Two Ramp mode:
```
TCD0.CTRLB |= TCD_WGMODE_TWORAMP_gc;
```
Since the TCD is a 12-bit timer/counter, it ranges from 0 to 4095 (4096 steps), corresponding to 0x000 to 0xFFF. For a 10% duty cycle, WOA must have an on time of 409 clock cycles (defined below by the ‘ON_TIME_CYCLES_WOA’ macro), corresponding to 0x199 in hexadecimal format:

$O N_T I M E_C Y C L E S_W O A = \frac{10}{100} \times 4096 = 409 = 0 x 199$

This means that the difference between the value of TCD0.CMPACLR and TCD0.CMPASET must be 409. In this use case example, the start of the on time for WOA will be 1023 (defined below by the ON_TIME_START_WOA macro).

$T C D 0. C M P A S E T = O N_T I M E_S T A R T_W O A = 1023 = 0 x 3 F F$ $T C D 0. C M P A C L R = O N_T I M E_S T A R T_W O A + O N_T I M E_C Y C L E S_W O A = 1023 + 409 = 1423 = 0 x 598$

For a 20% duty cycle, WOB must have an on time of 819 clock cycles (defined below by the ON_TIME_CYCLES_WOB macro), corresponding to 0x333 in hexadecimal format:

$O N_T I M E_C Y C L E S_W O B = \frac{20}{100} \times 4096 = 819 = 0 x 333$

This means that the difference between the value of TCD0.CMPBCLR and TCD0.CMPBSET must be 819. In this use case example, the start of the on time for WOB will be 1023 (defined below by the ON_TIME_START_WOB macro).

$T C D 0. C M P B S E T = O N_T I M E_S T A R T_W O B = 1023 = 0 x 3 F F$ $T C D 0. C M P B C L R = O N_T I M E_S T A R T_W O B + O N_T I M E_C Y C L E S_W O B = 1023 + 819 = 1842 = 0 x 732$

The following code snippet initializes TCD0.CMPASET, TCD0.CMPACLR, TCD0.CMPBSET, and TCD0.CMPBCLR with the corresponding values for generating the PWM signals with 10% and 20% duty cycles.
```
#define ON_TIME_START_WOA   0x3FF
#define ON_TIME_CYCLES_WOA  0x199
#define ON_TIME_START_WOB   0x3FF
#define ON_TIME_CYCLES_WOB  0x333

TCD0.CMPASET = ON_TIME_START_WOA;
TCD0.CMPACLR = ON_TIME_START_WOA + ON_TIME_CYCLES_WOA;
TCD0.CMPBSET = ON_TIME_START_WOB;
TCD0.CMPBCLR = ON_TIME_START_WOB + ON_TIME_CYCLES_WOB;
```
Enable the waveform channels as output.
The following code snippet enables the output channels and sets the waveform output to high:
```
_PROTECTED_WRITE(TCD0.FAULTCTRL, TCD_CMPAEN_bm | TCD_CMPA_bm
                               | TCD_CMPBEN_bm | TCD_CMPB_bm);
```
Check if the TCD is ready for enabling.
The following code snippet implements a wait until the TCD is ready to be enabled.
```
while (!(TCD0.STATUS & TCD_ENRDY_bm))
    {
        ;
    }
```
Select the input clock source and enable the TCD.
Figure 4-3. TCD0.CTRLA Register Configuration

The following code snippet will select OSCHF for the input frequency and will enable the TCD:
```
TCD0.CTRLA |= TCD_CLKSEL_PLL_gc | TCD_ENABLE_bm;
```
Tip: The full code example is also available in Appendix.

TB3236

4 Generating Two PWM Signals in Two Ramp Mode

Configuring the Main Clock

Configuring PA4 and PA5 Pins as Output

Configuring the TCD Input Clock and Operation Mode