2 Pin Descriptions

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table
Name	8‑Lead SOIC	8‑Lead TSSOP	8‑Pad UDFN⁽¹⁾	8‑Ball VFBGA	Function
A0⁽²⁾	1	1	1	1	Device Address Input
A1⁽²⁾	2	2	2	2	Device Address Input
A2⁽²⁾	3	3	3	3	Device Address Input
GND	4	4	4	4	Ground
SDA	5	5	5	5	Serial Data
SCL	6	6	6	6	Serial Clock
WP⁽²⁾	7	7	7	7	Write-Protect
V_CC	8	8	8	8	Device Power Supply

Note:

The exposed pad on this package can be connected to GND or left floating.
If the A0, A1, A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide variety of application environments, the pull‑down mechanism is intentionally designed to be somewhat strong. Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x V_CC), the pull‑down mechanism disengages. Microchip recommends connecting these pins to a known state whenever possible.