6.6.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic or logic instructions. For details about the bits in this register and how they are influenced by different instructions, see the Instruction Set Summary section.

Name:	SREG
Offset:	0x0F
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	I	T	H	S	V	N	Z	C
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – I Global Interrupt Enable Bit

Writing a ‘1’ to this bit enables interrupts on the device.

Writing a ‘0’ to this bit disables interrupts on the device, independent of the individual interrupt enable settings of the peripherals.

This bit is not cleared by hardware while entering an Interrupt Service Routine (ISR) or set when the RETI instruction is executed.

This bit can be set and cleared by software with the SEI and CLI instructions.

Changing the I bit through the I/O register results in a one-cycle Wait state on the access.

Bit 6 – T Transfer Bit

The bit copy instructions, Bit Load (BLD) and Bit Store (BST), use the T bit as source or destination for the operated bit.

Bit 5 – H Half Carry Flag

This flag is set when there is a half carry in arithmetic operations that support this, and is cleared otherwise. Half carry is useful in BCD arithmetic.

Bit 4 – S Sign Flag

This flag is always an Exclusive Or (XOR) between the Negative flag (N) and the Two’s Complement Overflow (V) flag.

Bit 3 – V Two’s Complement Overflow Flag

This flag is set when there is an overflow in arithmetic operations that support this, and is cleared otherwise.

Bit 2 – N Negative Flag

This flag is set when there is a negative result in an arithmetic or logic operation, and is cleared otherwise.

Bit 1 – Z Zero Flag

This flag is set when there is a zero result in an arithmetic or logic operation, and is cleared otherwise.

Bit 0 – C Carry Flag

This flag is set when there is a carry in an arithmetic or logic operation, and is cleared otherwise.

AVR64DA28/32/48/64