35.5.9 ASI System Status
| Name: | ASI_SYS_STATUS |
| Offset: | 0x0B |
| Reset: | 0x01 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERASEFAIL | SYSRST | INSLEEP | NVMPROG | UROWPROG | LOCKSTATUS | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 |
Bit 6 – ERASEFAIL Chip Erase Key Failed
1’ if the chip erase has failed. This bit is set to
‘0’ on Reset. A Reset held from the ASI_RESET_REQ register will
also affect this bit.Bit 5 – SYSRST System Reset Active
When this bit is set to ‘1’, there is an active
Reset on the system domain. When this bit is set to ‘0’, the
system is not in the Reset state.
This bit is set to ‘0’ on read.
A Reset held from the ASI_RESET_REQ register will also affect this bit.
Bit 4 – INSLEEP System Domain in Sleep
When this bit is set to ‘1’, the system domain is in the Idle or
deeper sleep mode. When this bit is set to ‘0’, the system is
not in any sleep mode.
Bit 3 – NVMPROG Start NVM Programming
When this bit is set to ‘1’, NVM programming can start from the
UPDI.
Reset the system through the UPDI Reset register when the UPDI is done.
Bit 2 – UROWPROG Start User Row Programming
When this bit is set to ‘1’, user row programming can start from
the UPDI.
When the User Row data have been written to the RAM, the UROWDONE bit in the ASI_SYS_CTRLA register must be written.
Bit 0 – LOCKSTATUS NVM Lock Status
When this bit is set to ‘1’, the device is locked.
If a chip erase is done, and the lock bits are set to ‘0’, this
bit will be read as ‘0’.