3.4.1 Output Compare Modulator in ATmega640/1280/1281/2560/2561

A clarification for the “Timing example in the Output Compare Modulator” has been made.

The following figure illustrates the modulator in action. In this example, the Timer/Counter1 is set to operate in fast PWM mode (non-inverted), and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1).

Figure 3-2. Output Compare Modulator, Timing Diagram

In this example, Timer/Counter0 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1.

The modulation has reduced the PWM signal (OC1C) resolution. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example, the resolution is reduced by a factor of two. The figure illustrates the reason for the reduction at the second and third periods of the PB7 output when PORTB7 equals zero. Period 2 high time is one cycle longer than period 3 high time, but the result on the PB7 output is equal in both periods.