33.5.3 Control A
| Name: | CTRLA |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IBDLY | PARD | DTD | RSD | GTVAL[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – IBDLY Inter-Byte Delay Enable
1’ to this bit enables a fixed-length inter-byte delay between
each data byte transmitted from the UPDI when doing multi-byte LD(S). The fixed
length is two IDLE bits. Bit 5 – PARD Parity Disable
1’ to this bit will disable the parity detection in the UPDI
by ignoring the Parity bit. This feature is recommended to be used only during
testing.Bit 4 – DTD Disable Time-Out Detection
1’ to this bit will disable the time-out detection on the PHY
layer, which requests a response from the ACC layer within a specified time (65536
UPDI clock cycles).Bit 3 – RSD Response Signature Disable
1’ to this bit will disable any response signatures generated
by the UPDI. This reduces the protocol overhead to a minimum when writing large
blocks of data to the NVM space. When accessing the system bus, the UPDI may
experience delays. If the delay is predictable, the response signature may be
disabled, otherwise loss of data may occur.Bits 2:0 – GTVAL[2:0] Guard Time Value
This bit field selects the guard time value that will be used by the UPDI when the transmission direction switches from RX to TX.
| Value | Description |
|---|---|
| 0x0 | UPDI guard time: 128 cycles (default) |
| 0x1 | UPDI guard time: 64 cycles |
| 0x2 | UPDI guard time: 32 cycles |
| 0x3 | UPDI guard time: 16 cycles |
| 0x4 | UPDI guard time: 8 cycles |
| 0x5 | UPDI guard time: 4 cycles |
| 0x6 | UPDI guard time: 2 cycles |
| 0x7 | Reserved |