26.3.4 Interrupts

Table 26-1. Available Interrupt Vectors and Sources
NameVector DescriptionConditions
SlaveTWI Slave interrupt
  • DIF: Data Interrupt Flag in TWIn.SSTATUS is set to ‘1’
  • APIF: Address or Stop Interrupt Flag in TWIn.SSTATUS is set to ‘1’
MasterTWI Master interrupt
  • RIF: Read Interrupt Flag in TWIn.MSTATUS is set to ‘1’
  • WIF: Write Interrupt Flag in TWIn.MSTATUS is set to ‘1’
When an interrupt condition occurs, the corresponding interrupt flag is set in the Master Status (TWIn.MSTATUS) register or the Slave Status (TWIn.SSTATUS) register.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed together into one combined interrupt request to the interrupt controller. The user must read the Interrupt flags from the TWIn.MSTATUS register or the TWIn.SSTATUS register, to determine which of the interrupt conditions are present.