35.8.5.3.6 FIFO Operation

For better system bus utilization, the I2C embeds up to 16-bytes FIFO capability. The receive / transmit buffer is considered to have the FIFO mode enabled when the FIFOEN bit in CTRLC register is set (CTRLC.FIFOEN = 1). By default, the FIFO can act as a 16-by-8-bit array, or as a 4-by-32-bit array, depending on the setting of the CTRLC.DATA32B bit.

The hardware around this array implements four pointers, called the CPU Write Pointer (CPUWRPTR), the CPU Read Pointer (CPURDPTR), the I2C Write pointer (I2CWRPTR) and the I2C Read pointer (I2CRDPTR). All of these pointers reset to ‘0’. The CPUWRPTR and CPURDPTR pointers are native to the CPU clock domain, while the I2CWRPTR and I2CRDPTR are native to the I2C domain. The location pointed to by the CPUWRPTR is the current TX FIFO. The location pointed to by the CPURDPTR becomes the current RX FIFO. Writes to DATA register by the CPU will point to TX FIFO. Reads to DATA register by the CPU will point to RX FIFO. The location pointed to by the I2CWRPTR / I2CRDPTR is logically the current shift register.

Figure 35-64. FIFO Overview

When using the I2C configured as Host, the Address register must be written with the desired address (ADDR.ADDR), and optionally, the transaction Length and transaction Length Enable bits (ADDR.LEN and ADDR.LENEN) can be written if the 32-bit extension is enabled (CTRLC.DATA32B).

In client operation, the Address Match interrupt in the Interrupt Flag Status and Clear register (INTFLAG.AMATCH) is set after the address is received, and the SCL clock is stretched as long as the FIFO is empty in host read mode.

The FIFO threshold settings allow (CTRLC.TXTRHOLD, CTRLC.RXTRHOLD) allow flexible interrupt, DMA trigger and bus condition generations, as described below.

The FIFO is fully accessible if the SERCOM is halted, by writing the corresponding CPU FIFO pointer in the FIFOPTR register. The RX or TX FIFO can be individually cleared, by setting the respective FIFO Clear bit in the Control B register (CTRLB.FIFOCLR). The FIFO Clear must be written before data transfer begins. Writing the FIFO Clear bits while a frame is in progress will produce unpredictable results.

Hardware Actions in Host Mode

Table 35-43. Interrupts Request Conditions for Valid SERCOM I2C Host Configurations
Direction CTRLB.SMENCTRLC.DATA32BLENGTH.LENENAction
Host Write 000
  • INTFLAG.TXFE = 1 if TX FIFO is empty
  • INTFLAG.TXFE = 1 if TX FIFO threshold reached
  • INTFLAG.MB = 1 if TX FIFO is empty and SCL hold
010
0 1 1
  • INTFLAG.TXFE = 1 if TX FIFO is empty
  • INTFLAG.TXFE = 1 if TX FIFO threshold is reached
  • INTFLAG.MB = 1 if TX FIFO is empty and SCL hold, or length transaction is completed
100
  • INTFLAG.TXFE = 1 if TX FIFO is empty
  • INTFLAG.TXFE = 1 if TX FIFO threshold reached
  • INTFLAG.MB = 1 if TX FIFO is empty and SCL hold, or length transaction is completed
110
111
Host Read 000
  • INTFLAG.SB = 1 if RX FIFO is full
  • INTFLAG.RXFE = 1 if RX FIFO threshold reached or length transaction is completed
010
011
100
110
111
Table 35-44. Bus Actions for Valid SERCOM I2C Host Configurations
Direction CTRLB.SMENCTRLC.DATA32BLENGTH.LENENActions
Host Write 000
  • SCL hold if TX FIFO is empty
010
0 1 1
  • SCL hold if TX FIFO is empty and length transaction not completed
  • Issue STOP when transaction is completed
1 0 0
  • SCL hold if TX FIFO is empty, when no automatic stop is sent
  • STOP is sent on SW decision
1 1 0
  • SCL hold if TX FIFO is empty, when no automatic stop is sent
  • STOP is sent on SW decision
1 1 1
  • SCL hold if TX FIFO is empty and length transaction is not completed
  • Issue STOP when transaction is completed
Host Read 000
  • SCL hold if RX FIFO is full
010
  • SCL hold if RX FIFO is full
0 1 1
  • SCL stretched if RX FIFO is full
  • ACK/NACK last frame byte, depending on Acknowledge Action (CTRLB.ACKACT)
  • ACK all other bytes
100
  • SCL stretched if RX FIFO is full
110
1 1 1
  • SCL stretched if RX FIFO is full
  • ACK/NACK last frame byte, depending on Acknowledge Action (CTRLB.ACKACT)
  • ACK all other bytes

Hardware Actions in Client Mode

Table 35-45. Interrupt Request Conditions for Valid SERCOM I2C Client Configurations
Direction CTRLB.SMENCTRLC.DATA32BLENGTH.LENENCondition
Host Write 000
  • INTFLAG.DRDY = 1 if RX FIFO is full
  • INTFLAG.RXFF = 1 RX FIFO threshold is reached or length transaction is completed
010
011
100
110
111
Host Read 000
  • INTFLAG.DRDY = 1 if TX FIFO is empty and SCL hold
  • INTFLAG.TXFE = 1 if TX FIFO is empty or TX FIFO threshold is reached
010
011
100
110
111
Table 35-46. Bus Actions for Valid SERCOM I2C Client Configurations
Direction CTRLB.SMENCTRLC.DATA32BLENGTH.LENENActions
Host Write 0 0 0
  • Byte mode operation
  • SCL stretched if RX FIFO is full
0 1 0
  • 32-bit mode operation
  • SCL stretched if RX FIFO is full
  • ACK/NACK each 4th byte, depending on Acknowledge Action (CTRLB.ACKACT)
  • ACK all other bytes
0 1 1
  • 32-bit mode operation with length control
  • SCL stretched if RX FIFO is full
  • ACK/NACK last byte of the frame, depending on Acknowledge Action (CTRLB.ACKACT)
  • ACK all other bytes
1 0 0
  • SCL stretched if RX FIFO is full
  • ACK all bytes received
1 1 0
  • 32-bit mode operation
  • SCL stretched if RX FIFO is full
  • ACK/NACK each 4th byte, depending on Acknowledge Action (CTRLB.ACKACT)
  • ACK all other bytes
1 1 1
  • 32-bit mode operation with length control
  • SCL stretched if RX FIFO is full
  • ACK/NACK last byte of the frame, depending on Acknowledge Action (CTRLB.ACKACT)
  • ACK all other bytes
Host Read 000
  • SCL stretched if TX FIFO is empty
010
  • SCL stretched if TX FIFO is empty
011
  • SCL stretched if TX FIFO is empty and length transaction is not completed
100
  • SCL stretched if TX FIFO is empty
110
  • SCL stretched if TX FIFO is empty
111
  • SCL stretched if TX FIFO is empty and length transaction is not completed