22.12.4 TxGATE

Timer Gate Source Selection Register

Name:	TxGATE
Offset:	0x0310


Bit	7	6	5	4	3	2	1	0
				GSS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – GSS[4:0] Timer Gate Source Selection

Table 22-5. Timer Gate Sources
GSS	Gate Source
`11111`	Reserved
`11110`	CLB_BLE[5]
`11101`	CLB_BLE[4]
`11100`	CLB_BLE[3]
`11011`	CLB_BLE[2]
`11010`	PWM2_OUT
`11001`	PWM1_OUT
`11000`	CLC4_OUT
`10111`	CLC3_OUT
`10110`	CLC2_OUT
`10101`	CLC1_OUT
`10100`	Reserved
`10011`	C2_OUT
`10010`	C1_OUT
`10001-01001`	Reserved
`01000`	CCP2_OUT
`00111`	CCP1_OUT
`00110-00100`	Reserved
`00011`	TMR2_Postscaled_OUT
`00010`	Reserved
`00001`	TMR0_overflow_OUT
`00000`	Pin selected by T1GPPS

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