6 Core Independent Peripherals

Core Independent Peripherals (CIPs) are peripherals designed to handle their tasks without any intervention from the CPU, freeing the CPU to do other tasks in parallel or, for our purposes, enter a low-power mode. Other advantages of CIPs include providing short and predictable response times between peripherals and reducing the complexity and execution time of the software. In Event System we have already seen an example of a CIP. Other examples include Configurable Custom Logic (CCL), Timer/Counter A and B (TCA/TCB), Real Timer Counter (RTC), Analog-to-Digital Converter (ADC) and CRCSCAN.

Some peripherals can process incoming data without waking the CPU. Depending on the incoming data, the peripherals can decide if the CPU should wake up, or if there is no further action to take. Two examples of such peripherals are the Two-Wire Interface (TWI) and the ADC. The TWI supports Wake on Address Match, where it examines the start of an incoming data frame, and only wakes the CPU if the address of the incoming frame matches its own address. The ADC supports Window mode, where each sample is compared with two values, representing a window. Based on configuration, the ADC can wake the CPU if the sample is below, above, inside, or outside the window.