1.3 Runtime Calibration Using a 32.768 kHz Reference Clock

The XMEGA Clock System provides two DFLLs, one for the 2 MHz RC oscillator and one for the 32 MHz RC oscillator. The DFLLs can be configured individually to use either the internal 32.768 kHz RC oscillator or an external 32.768 kHz watch crystal as a reference for the calibration process.

Once enabled, a DFLL provides continuous calibration of its oscillator based on the clock reference. When entering Sleep mode, the current state is frozen and the calibration loop continues from where it stopped when exiting from Sleep mode again.

If a DFLL is disabled, the current calibration value for the oscillator will remain in effect until the DFLL is enabled again and the calibration process continues.

For more information please refer to the device data sheet and application note AVR1003 Using the XMEGA Clock System.