22.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x0D8

Bit 76543210 
  D1S[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxx 

Bits 6:0 – D1S[6:0] CLCn Data1 Input Selection

Table 22-2. CLC Input Selection
DyS Input Source DyS (cont.) Input Source (cont.)
[0] 0000 0000 CLCIN0PPS [26] 0001 1010 PWM3S1P2_OUT
[1] 0000 0001 CLCIN1PPS [27] 0001 1011 NCO1
[2] 0000 0010 CLCIN2PPS [28] 0001 1100 CMP1_OUT
[3] 0000 0011 CLCIN3PPS [29] 0001 1101 CMP2_OUT
[4] 0000 0100 FOSC [30] 0001 1110 ZCD
[5] 0000 0101 HFINTOSC(1) [31] 0001 1111 IOC
[6] 0000 0110 LFINTOSC(1) [32] 0010 0000 DSM1
[7] 0000 0111 MFINTOSC(1) [33] 0010 0001 HLVD_OUT
[8] 0000 1000 MFINTOSC (32 kHz)(1) [34] 0010 0010 CLC1
[9] 0000 1001 SFINTOSC (1 MHz)(1) [35] 0010 0011 CLC2
[10] 0000 1010 SOSC(1) [36] 0010 0100 CLC3
[11] 0000 1011 EXTOSC(1) [37] 0010 0101 CLC4
[12] 0000 1100 ADCRC(1) [38] 0010 0110 U1TX
[13] 0000 1101 CLKR [39] 0010 0111 U2TX
[14] 0000 1110 TMR0 [40] 0010 1000 U3TX
[15] 0000 1111 TMR1 [41] 0010 1001 SPI1_SDO
[16] 0001 0000 TMR2 [42] 0010 1010 SPI1_SCK
[17] 0001 0001 TMR3 [43] 0010 1011 SPI1_SS
[18] 0001 0010 TMR4 [44] 0010 1100 SPI2_SDO
[19] 0001 0011 SMT1 [45] 0010 1101 SPI2_SCK
[20] 0001 0100 CCP1 [46] 0010 1110 SPI2_SS
[21] 0001 0101 PWM1S1P1_OUT [47] 0010 1111 I2C_SCL
[22] 0001 0110 PWM1S1P2_OUT [48] 0011 0000 I2C_SDA
[23] 0001 0111 PWM2S1P1_OUT [49] 0011 0001 CWG1A
[24] 0001 1000 PWM2S1P2_OUT [50] 0011 0010 CWG1B
[25] 0001 1001 PWM3S1P1_OUT [51] 0011 0011 -
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxxx
All Other Resets = uuuuuuu