The standard PIC18 instruction set has six two-word instructions:
CALL, MOVFF, GOTO,
LFSR, MOVSF and MOVSS and two
three-word instructions: MOVFFL and MOVSFL. In all cases,
the second and the third word of the instruction always has 1111 as its
four Most Significant bits; the other 12 bits are literal data, usually a data memory
address.
The use of 1111 in the four MSbs of an instruction
specifies a special form of NOP. If the instruction is executed in proper
sequence, immediately after the first word, the data in the second word is accessed and
used by the instruction sequence. If the first word is skipped for some reason and the
second word is executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is preceded by a conditional instruction
that changes the PC.
Table 7-3 and Table 7-4 show more details of how two-word instructions work. Table 7-5 and Table 7-6 show more details of how three-word instructions work.
Important: See the “PIC18 Instruction Execution and
the Extended Instruction Set” section for information on two-word instructions in
the extended instruction set.
Table 7-3. Two-Word Instructions (Case
1)
| Object Code |
Source Code |
Comment |
0110 0110 0000 0000 |
TSTFSZ REG1 |
; is RAM location 0? |
1100 0001 0101 0011 |
MOVFF REG1,REG2 |
; No, skip this word |
1111 0100 0101 0110 |
|
; Execute this word as NOP |
0010 0100 0000 0000 |
ADDWF REG3 |
; continue code |
Table 7-4. Two-Word Instructions (Case
2)
| Object Code |
Source Code |
Comment |
0110 0110 0000 0000 |
TSTFSZ REG1 |
; is RAM location 0? |
1100 0001 0101 0011 |
MOVFF REG1,REG2 |
; Yes, execute this word |
1111 0100 0101 0110 |
|
; 2nd word of instruction |
0010 0100 0000 0000 |
ADDWF REG3 |
; continue code |
Table 7-5. Three-Word Instructions (Case
1)
| Object Code |
Source Code |
Comment |
0110 0110 0000 0000 |
TSTFSZ REG1 |
; is RAM location 0? |
0000 0000 0110 0000 |
MOVFFL REG1,REG2 |
; Yes, skip this word |
1111 0100 1000 1100 |
|
; Execute this word as NOP |
1111 0100 0101 0110 |
|
; Execute this word as NOP |
0010 0100 0000 0000 |
ADDWF REG3 |
; continue code |
Table 7-6. Three-Word Instructions (Case
2)
| Object Code |
Source Code |
Comment |
0110 0110 0000 0000 |
TSTFSZ REG1 |
; is RAM location 0? |
0000 0000 0110 0000 |
MOVFFL REG1,REG2 |
; No, execute this word |
1111 0100 1000 1100 |
|
; 2nd word of instruction |
1111 0100 0101 0110 |
|
; 3rd word of instruction |
0010 0100 0000 0000 |
ADDWF REG3 |
; continue code |
