12.5.9 FSCMCON

Fail-Safe Clock Monitor Control and Status Register

Note:

This bit is used to demonstrate that FSCM can detect clock failure; the bit must be cleared for normal operation.
This bit will not be cleared by hardware upon clock recovery; the bit must be cleared by the user.

Name:	FSCMCON
Address:	0x458


Bit	7	6	5	4	3	2	1	0
			FSCMSFI	FSCMSEV	FSCMPFI	FSCMPEV	FSCMFFI	FSCMFEV
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bit 5 – FSCMSFI SOSC Fail-Safe Clock Monitor Fault Injection⁽¹⁾

Value	Description
1	SOSC FSCM clock input is blocked; FSCM will time-out
0	SOSC FSCM clock input is enabled; FSCM functions as indicated

Bit 4 – FSCMSEV SOSC Fail-Safe Clock Monitor Status⁽²⁾

Value	Description
1	SOSC clock showed a failure
0	FSCM is detecting SOSC input clocks, or the bit was cleared by the user

Bit 3 – FSCMPFI Primary Oscillator Fail-Safe Clock Monitor Fault Injection⁽¹⁾

Value	Description
1	Primary Oscillator FSCM clock input is blocked; FSCM will time-out
0	Primary Oscillator FSCM clock input is enabled; FSCM functions as indicated

Bit 2 – FSCMPEV Primary Oscillator Fail-Safe Clock Monitor Status⁽²⁾

Value	Description
1	Primary Oscillator clock showed a failure
0	FSCM is detecting primary oscillator input clocks, or the bit was cleared by the user

Bit 1 – FSCMFFI FOSC Fail-Safe Clock Monitor Fault Injection⁽¹⁾

Value	Description
1	F_OSC FSCM clock input is blocked; FSCM will time-out
0	F_OSC FSCM clock input is enabled; FSCM functions as indicated

Bit 0 – FSCMFEV FOSC Fail-Safe Clock Monitor Status⁽²⁾

Value	Description
1	F_OSC clock showed a failure
0	FSCM is detecting F_OSC input clocks, or the bit was cleared by the user

This bit is used to demonstrate that FSCM can detect clock failure; the bit must be cleared for normal operation. This bit will not be cleared by hardware upon clock recovery; the bit must be cleared by the user.