36.4.2.2 Host Clock Timing

The Serial Clock (SCL) signal is generated by module hardware via the I2C Clock Selection (I2CxCLK) Register, the I2C Baud Rate Prescaler (I2CxBAUD) Register, and the Fast Mode Enable (FME) bit.

The figure below illustrates the SCL clock generation.

Figure 36-29. SCL Clock Generation

I2CxCLK contains several clock source selections. The clock source selections typically include variants of the system clock and timer resources.

Important: When using a timer as the clock source, the timer must also be configured. Additionally, when using the HFINTOSC as a clock source, it is important to understand that the HFINTOSC frequency selected by the OSCFRQ register is used as the clock source. The clock divider selected by the NDIV bits is not used. For example, if OSCFRQ selects 4 MHz as the HFINTOSC clock frequency, and the NDIV bits select a divide by four scaling factor, the I2C Clock Frequency will be 4 MHz and not 1 MHz since the divider is ignored.

I2CxBAUD is used to determine the prescaler (clock divider) for the I2CxCLK source.

The FME bit acts as a secondary divider to the prescaled clock source.

When FME is clear (FME = 0), one SCL period (TSCL) is equal to five clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by five. For example, if the HFINTOSC (set to 4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and the FME bit is clear, the actual SCL frequency is 100 kHz (see the equation below).

Equation 36-1. SCL Frequency (FME = 0)
Example:
  • I2CxCLK: HFINTOSC (4 MHz)
  • I2CxBAUD: 7
  • FME: FME = 0
f S C L =   f I 2 C x C L K ( B A U D ⁢ +   1 ) F M E ⁢ = 4 ⁢     M H z 8 5 ⁢   =   100 ⁢     k H z  

When FME is clear, host hardware uses the first prescaled I2CxCLK source period to drive SCL low (see Figure 36-30). During the second period, hardware verifies that SCL is in fact low. During the third period, hardware releases SCL, allowing it to float high. Host hardware then uses the fourth and fifth periods to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the fourth and/or fifth period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next two I2CxCLK periods to verify that SCL is high.

Figure 36-30. SCL Timing (FME = 0)

When FME is set (FME = 1), one SCL period (TSCL) is equal to four clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by four. Using the example from above, if the HFINTOSC (4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and the FME bit is set, the actual SCL frequency is 125 kHz (see the equation below).

Equation 36-2. SCL Frequency (FME = 1)
Example:
f S C L =   f I 2 C x C L K ( B A U D ⁢ +   1 ) F M E ⁢ = 4 ⁢     M H z 8 4 ⁢   =   125 ⁢     k H z  

When FME is set, host hardware uses the first prescaled I2CxCLK source period to drive SCL low (see Figure 36-31). During the second prescaled period, hardware verifies that SCL is in fact low. During the third period, hardware releases SCL, allowing it to float high. Host hardware then uses the fourth period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the fourth period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next period to verify that SCL is high.

Figure 36-31. SCL Timing (FME = 1)