28.3.1.7 Sequencer Logic

Each LUT pair can be connected to a sequencer. The sequencer can function as either D flip-flop, JK flip-flop, gated D latch, or RS latch. The function is selected by writing the Sequencer Selection (SEQSEL) bit group in the Sequencer Control (CCL.SEQCTRLn) register.

The sequencer receives its input from either the LUT, filter or edge detector, depending on the configuration.

A sequencer is clocked by the same clock as the corresponding even LUT. The clock source is selected by the Clock Source (CLKSRC) bit group in the LUT n Control A (CCL.LUTnCTRLA) register.

The flip-flop output (OUT) is refreshed on the rising edge of the clock. When the even LUT is disabled, the latch is cleared asynchronously. The flip-flop Reset signal (R) is kept enabled for one clock cycle.

Gated D Flip-Flop (DFF)

The D input is driven by the even LUT output, and the G input is driven by the odd LUT output.

Figure 28-7. D Flip-Flop
Table 28-4. DFF Characteristics
RGDOUT
1XXClear
011Set
010Clear
00XHold state (no change)

JK Flip-Flop (JK)

The J input is driven by the even LUT output, and the K input is driven by the odd LUT output.

Figure 28-8. JK Flip-Flop
Table 28-5. JK Characteristics
RJKOUT
1XXClear
000Hold state (no change)
001Clear
010Set
011Toggle

Gated D Latch (DLATCH)

The D input is driven by the even LUT output, and the G input is driven by the odd LUT output.

Figure 28-9. D Latch
Table 28-6. D Latch Characteristics
GDOUT
0XHold state (no change)
10Clear
11Set

RS Latch (RS)

The S input is driven by the even LUT output, and the R input is driven by the odd LUT output.

Figure 28-10. RS Latch
Table 28-7. RS Latch Characteristics
SROUT
00Hold state (no change)
01Clear
10Set
11Forbidden state