20.5.2 Status

Name: STATUS
Offset: 0x01
Reset: 0x00
Property: Configuration Change Protection

Bit 76543210 
 LOCK      SYNCBUSY 
Access R/WR 
Reset 00 

Bit 7 – LOCK Lock

Writing this bit to ‘1’ write-protects the WDT.CTRLA register.

It is only possible to write this bit to ‘1’. This bit can be cleared in Debug mode only.

If the PERIOD bits in WDT.CTRLA are different from zero after boot code, the lock will automatically be set.

This bit is under CCP.

Bit 0 – SYNCBUSY Synchronization Busy

This bit is set after writing to the WDT.CTRLA register, while the data is being synchronized from the peripheral clock domain to the WDT clock domain.

This bit is cleared after the synchronization is finished.

This bit is not under CCP.