Jump to main content
tinyAVR® 2 Family ATtiny3224/3226/3227
Search
Product Pages
ATtiny3224
ATtiny3226
ATtiny3227
Home
36
Package Drawings
36.7
20-Pin VQFN
ATtiny3224/3226/3227
Introduction
tinyAVR® 2 Family Overview
Features
1
Block Diagram
2
Pinout
3
I/O Multiplexing and Considerations
4
Hardware Guidelines
5
Conventions
6
AVR® CPU
7
Memories
8
Peripherals and Architecture
9
General Purpose I/O Registers
10
NVMCTRL - Nonvolatile Memory Controller
11
CLKCTRL - Clock Controller
12
SLPCTRL - Sleep Controller
13
RSTCTRL - Reset Controller
14
CPUINT - CPU Interrupt Controller
15
EVSYS - Event System
16
PORTMUX - Port Multiplexer
17
PORT - I/O Pin Configuration
18
BOD - Brown-out Detector
19
VREF - Voltage Reference
20
WDT - Watchdog Timer
21
TCA - 16-bit Timer/Counter Type A
22
TCB - 16-Bit Timer/Counter Type B
23
RTC - Real-Time Counter
24
USART - Universal Synchronous and Asynchronous Receiver and Transmitter
25
SPI - Serial Peripheral Interface
26
TWI - Two-Wire Interface
27
CRCSCAN - Cyclic Redundancy Check Memory Scan
28
CCL - Configurable Custom Logic
29
AC - Analog Comparator
30
ADC - Analog-to-Digital Converter
31
UPDI - Unified Program and Debug Interface
32
Instruction Set Summary
33
Electrical Characteristics
34
Typical Characteristics
35
Ordering Information
36
Package Drawings
36.1
Online Package Drawings
36.2
Package Marking Information
36.3
14-Pin SOIC
36.4
14-Pin TSSOP
36.5
20-Pin SOIC
36.6
20-Pin SSOP
36.7
20-Pin VQFN
36.8
20-Pin VQFN Wettable Flanks
36.9
24-Pin VQFN
36.10
24-Pin VQFN Wettable Flanks
37
Data Sheet Revision History
The Microchip Website
Product Change Notification Service
Customer Support
Product Identification System
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service
36.7 20-Pin VQFN
