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tinyAVR® 2 Family ATtiny3224/3226/3227

ATtiny3224 ATtiny3226 ATtiny3227

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11 CLKCTRL - Clock Controller
11.5 Register Description

ATtiny3224/3226/3227

Introduction
tinyAVR® 2 Family Overview
Features
1 Block Diagram
2 Pinout
3 I/O Multiplexing and Considerations
4 Hardware Guidelines
5 Conventions
6 AVR® CPU
7 Memories
8 Peripherals and Architecture
9 General Purpose I/O Registers
10 NVMCTRL - Nonvolatile Memory Controller
11 CLKCTRL - Clock Controller
- 11.1 Features
- 11.2 Overview
- 11.3 Functional Description
- 11.4 Register Summary
- 11.5 Register Description
  - 11.5.1 Main Clock Control A
    Main Clock Control A
  - 11.5.2 Main Clock Control B
    Main Clock Control B
  - 11.5.3 Main Clock Lock
    Main Clock Lock
  - 11.5.4 Main Clock Status
    Main Clock Status
  - 11.5.5 20 MHz Oscillator Control A
    20 MHz Oscillator Control A
  - 11.5.6 20 MHz Oscillator Calibration A
    20 MHz Oscillator Calibration A
  - 11.5.7 20 MHz Oscillator Calibration B
    20 MHz Oscillator Calibration B
  - 11.5.8 32.768 kHz Oscillator Control A
    32.768 kHz Oscillator Control A
  - 11.5.9 32.768 kHz Crystal Oscillator Control A
    32.768 kHz Crystal Oscillator Control A
12 SLPCTRL - Sleep Controller
13 RSTCTRL - Reset Controller
14 CPUINT - CPU Interrupt Controller
15 EVSYS - Event System
16 PORTMUX - Port Multiplexer
17 PORT - I/O Pin Configuration
18 BOD - Brown-out Detector
19 VREF - Voltage Reference
20 WDT - Watchdog Timer
21 TCA - 16-bit Timer/Counter Type A
22 TCB - 16-Bit Timer/Counter Type B
23 RTC - Real-Time Counter
24 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
25 SPI - Serial Peripheral Interface
26 TWI - Two-Wire Interface
27 CRCSCAN - Cyclic Redundancy Check Memory Scan
28 CCL - Configurable Custom Logic
29 AC - Analog Comparator
30 ADC - Analog-to-Digital Converter
31 UPDI - Unified Program and Debug Interface
32 Instruction Set Summary
33 Electrical Characteristics
34 Typical Characteristics
35 Ordering Information
36 Package Drawings
37 Data Sheet Revision History
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11.5 Register Description

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