16.3.6 Additional References

For more information on DDR and SerDes, see the following.

Table 16-546. Additional References
Core NameLink
DDR RTG4 FPGA DDR Memory Controller User Guide

RTG4 DDR Memory Controller Configuration User Guide

RTG4 DDR Memory Controller with Initialization Configuration User Guide

SerDes RTG4 FPGA High-Speed Serial Interfaces User Guide

RTG4 High Speed Serial Interface Configuration User Guide

AMBAIF_SRAM RTG4_SRAM_AHBL_AXI User Guide

CCC

CCCAPB

 RTG4 FPGA Clock Conditioning Circuit with PLL Configuration User Guide
DPRAM RTG4 FPGA Dual-Port Large SRAM Configuration User Guide
FDDR RTG4 DDR Memory Controller Configuration User Guide
FDDR_INIT RTG4 DDR Memory Controller with Initialization Configuration User Guide

NPSS_SERDES_IF

NPSS_SERDES_IF_INIT

PCIE_SERDES_IF

PCIE_SERDES_IF_INIT

 RTG4 High Speed Serial Interface Configuration User Guide
RTG4FCCC_ELOCK RTG4 FCCC with Enhanced PLL Calibration Configurator User Guide
RTG4FCCC_ELOCK RTG4 FCCC with Enhanced PLL Calibration Configurator Release Notes
TPRAM RTG4 FPGA Two-Port Large SRAM Configuration User Guide
UPROM RTG4 μPROM Configuration User Guide
URAM RTG4 Micro SRAM Configuration User Guide