1.1 Libero® SoC Design Suite v2026.1 Welcome Page

RTG4

• System Controller Suspend Mode (SCSM): Changed the default setting to "ON" and moved the option to ‘Project Settings > Device Settings’. It helps align the default configuration with the recommended suspend-mode usage across RTG4, RT PolarFire, and RT PolarFire SoC. Pre-existing RTG4 designs that did not employ SCSM will be prompted to enable SCSM when opened in v2026.1, and the user must review the Programming Bitstream options to ensure it meets their required settings.
• One-Time Programmable (OTP): For designs employing the OTP option, there are additional options available, such as customizing which remaining JTAG actions are permitted with OTP, as well as enabling SCSM and OTP at the same time, with no further JTAG access possible.
• PCIE_SERDES_IF: Enhanced reset handling for CoreABC-based reset flows.

RT PolarFire SoC

• PFSOC_TAMPER: Disabled the unsupported "Fabric Digest Check" option when "Fabric POR Digest Check" is selected for RT PolarFire SoC devices that do not support it. The GUI now provides guidance for alternative digest-check methods such as external JTAG/SPI VERIFY_DIGEST, system controller Digest Check service followed by device reset, or IAP_VERIFY service.

New Device Support

• RT PolarFire timing data: Updated MIL timing data for the following supported devices from Preliminary to Production for STD and -1 speed grades:
  • RTPF500ZT/ZTS/ZTL/ZTLS
  • RTPFS160ZT/ZTS/ZTL/ZTLS
  • RTPFS460ZT/ZTS/ZTL/ZTLS

• Simulator:
  • QuestaSim ME and ModelSim ME Pro upgraded to 2025.3 version.
  • QuestaSim ME is now the default simulator, while ModelSim ME Pro is available as an optional simulator.
  • Simulation compile control: Added support for passing custom arguments to vlog and vcom commands, giving users more control over Verilog and VHDL compilation options during simulation.
• Remote Programming Server: Added Remote Programming Server support for Libero SoC and FPExpress, allowing users to configure and use programming hardware connected to a remote machine while preserving existing workstation-mode behavior.
• Standalone SmartDebug remote workflows: Added remote programming and debug support in standalone SmartDebug, including remote server connections, programmer management, chain construction and scanning, programming actions, debug features, and multi-client usage.
• Netlist Viewer: Enhanced the Netlist Viewer to display initialization strings for CFG macros.
• Tcl export flow: Improved hierarchical export of component descriptions to Tcl by addressing HDL folder handling issues.
• SmartDesign Tcl: Improved sd_create_pin_group handling when moving an existing pin-group member to another group.
• Synplify Pro ME and Identify tools upgraded to Y-2026.03M version.
• Platform OS: Extended support to RHEL 9, AlmaLinux 9 and Ubuntu 24.04.

PolarFire, RT PolarFire, PolarFire SoC and RT PolarFire SoC Enhancements

• Enhanced Transceiver simulation model:
  • Introduced fast-lock simulation to support fast lock-time simulation behavior, helping reduce simulation time while preserving expected initialization behavior.
  • Added support for providing greater flexibility for simulating transceiver configurations where transmit and receive lanes are used independently to support independent TX and RX lane operation.
• PF_IOD Post-Layout Simulation: Added post-layout gate-level functional simulation support for statically delayed PF_IOD resources.
• PF_IOD initial tap value simulation: Added startup or initial tap value support for PF_IOD post-layout simulation.
• PF_IOD_OCTAL_DDR: Improved clock frequency display by showing the rounded frequency for the CCC PLL Output 3 clock divider label.
• PF_IOD_GENERIC_RX: Enhanced guidance for data rate versus fabric clock speed configuration.
• PF_XCVR clocking: Enhanced PF_XCVR support for designs using a mix of global and regional clocks.
• PF_PCIE: Updated UIC initialization for PCIe Gen2x1 configurations using -6 dB de-emphasis.
• PF_Crypto: Updated tooltip and parameter-description guidance for AHB clock frequency requirements. The guidance clarifies that the AHB clock must be greater than or equal to 125 MHz when the embedded DLL is enabled and less than or equal to 70 MHz when the embedded DLL is disabled.
• PF_DDR: Added a warning when I/O Calibration is not enabled for banks using memory interfaces.
• Periphery pre-placement checks: Added pre-placement checks for periphery resources to identify placement issues earlier in the design flow.
• Routability improvements: Improved routability for designs where global signals drive wide-mux structures.
• Clock-source validation: Added a DRC when CLK_FROM_RCOSC_160MHZ pin on the TAMPER or INIT_MONITOR component is not driven by the RCOSC, helping users detect clock-source configuration issues earlier.
• Silver license expansion: Upgraded Silver license support for the following devices:
  • MPF300TS-1FCG1152I
  • MPF200TC: FCG1152I, FCG1152E, FCVG484E

PolarFire SoC, RT PolarFire SoC Enhancements

• MSS DDR impedance display: Added display of the configured MSS DDR impedance value in ohms in the “MSS Impedance (Ohm)” column.
• eNVM configuration: Added support for plain-text data clients in the eNVM configuration flow.

RTG4 Enhancements

• PROBE_READ_DATA pin: Enabled the layout log to print the I/O settings for the PROBE_READ_DATA output pin when selected.
• Compressed DAT files: Added compressed bitstream support during RTG4 DAT file generation to help reduce generated DAT file size for supported programming flows.

PolarFire SoC Standalone MSS Configurator

• Physical Memory Protection: Added Design Rule Checks for PMP and MPU expert mode fields in batch mode to prevent MSS generation for invalid values.
• MSS DDR timing: Updated MSS DDR configuration to account for the tCCD_L memory timing parameter.
• MSS Timing Shell export: Added support to export MSS Timing Shell information when HDL export is enabled.

SmartHLS™

• Default Simulator Updated in IDE: Updated the default simulator tool path in the SmartHLS IDE to QuestaSim ME Pro instead of ModelSim ME Pro from the same Libero installation.
• No User-Visible Impact: No new functional enhancements or behavioral changes have been introduced. Existing users are not expected to experience any impact, and no action is required as a result of this update.