1.3 SmartHLS 2026.1

Release Date: June 2026

Software Features and Enhancements

Default Simulator Updated in IDE
In the SmartHLS IDE, the default initialized Simulator tool path has been updated to point to QuestaSim ME Pro instead of ModelSim ME Pro from the same Libero® installation.
No User-Visible Impact
This release does not introduce any functional enhancements or behavioral changes. Existing users are not expected to experience any impact, and no action is required as a result of this update.

Resolved Issues

  • Fixed a crash that occurred when error message SHLS-55 was triggered.
  • Removed an incorrect SmartHLS IP simulation libraries recompilation warning message that appeared after updating the simulator path in the IDE.
  • Fixed a scheduling bug that occurred when an AXI4 master interface, implemented using SmartHLS's C++ AXI interface library (hls/axi_interface.hpp), was used in a pipelined function in designs that also contain pipelined loops.
  • Fixed Verilog code generation for multi-top designs that require runtime memory address resolution.
  • Fixed Verilog code generation for designs in which a non-struct data FIFO was present at the top-level interface but unused in the code.
  • Conditionally resolved an issue where mixed C/C++ input designs failed to compile in SmartHLS. Compilation now succeeds provided the HLS Makefile variable CXX_STANDARD is not customized.
  • Fixed timing violation checks to cover both setup/max and hold/min violations. Timing failures are now treated as errors by default to prevent the unintended use of timing-failed bitstreams on hardware.
  • Adjusted the default Place-and-Route (PnR) options used in the MiV_SoC project to improve timing closure.