1 Multi-Voltage I/O (MVIO) Overview

The Multi-Voltage I/O (MVIO) module provides a group of I/O pins powered from an alternative voltage domain separate from VDD. Similar to how standard I/O pins run and operate based on the voltage supplied using the VDD supply pin(s) of the device, the MVIO pins run and operate based on their voltage supplied using the VDDIOx supply pin(s) of the device. The VIL/VIH and VOL/VOH voltage levels on MVIO pins scale based on the VDDIOx voltage, allowing them to have the same digital functionality as standard I/O pins on the VDD domain, including GPIO, serial communication, Pulse-Width Modulation, and PPS functionality for PIC devices. Additionally, the MVIO voltage domain(s) will remain operational in Sleep mode and when the CPU is halted in Debug mode as long as the corresponding VDDIOx supply voltage remains active. Refer to the electrical specifications section of the device data sheet for more information.
Attention: Not all device families that offer MVIO support analog functionality on those pins. Refer to the data sheet for more information.
The MVIO module can provide multiple alternative voltage domains associated with a select group of pins, so it is important to refer to the device data sheet for more information about how many voltage domains are available on each device family and pins dedicated to each domain. To determine how many voltage domains are available and which pins lie within each MVIO domain, refer to the “Pin Diagrams” or “Pinout” section of the device data sheet. The provided pin diagrams in the data sheet give a visual representation showing where each power supply pin is (VDD and all VDDIOx pins), and which voltage domain each I/O pin operates from for every available package within that specific device family. Figure 1-1 and Figure 1-2 are examples of the pin diagrams for a PIC device and an AVR device respectively, with MVIO for reference.
Figure 1-1. 28-Pin SPDIP, SSOP and SOIC from PIC18F26/45/46/55/56Q24 Device Data Sheet
Figure 1-2. 48-pin VQFN and TQFP from AVR128DB28/32/48/64 Device Data Sheet