8.1 Terminology

A technique in which a clock signal is sent out by Multi-ICE and waits for the returned clock before generating the next clock pulse. The technique allows the Multi-ICE interface unit to adapt to differing signal drive capabilities and differing cable lengths.

A specification of a set of procedures, functions, data structures, and constants that are used to interface two or more software components together.

Memory organization where the least significant byte of a word is at a higher address than the most significant byte. See Little-endian.

The process of writing dirty data in a cache to main memory.

An additional processor that is used for certain operations, for example, for floating-point math calculations, signal processing, or memory management.

When referring to a processor data cache, data that has been written to the cache but has not been written to main memory. Only write-back caches can have dirty data, because a write-through cache writes data to the cache and to main memory simultaneously. The process of writing dirty data to main memory is called cache cleaning.

A collection of programs, any of which can be called when needed by an executing program. A small program that helps a larger program communicate with a device such as a printer or keyboard is often packaged as a DLL.

The additional hardware provided by debug-able ARM processors to aid debugging.

A 16-bit unit of information. Contents are taken as being an unsigned integer, unless otherwise stated.

A computer which provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.

Instruction cache.

A hardware extension to the EmbeddedICE logic that provides more breakpoint units.

Identifier.

The IEEE Standard, which defines TAP. Commonly (but incorrectly) referred to as JTAG.

An executable file that has been loaded onto a processor for execution.

A device enabling access to and modification of the signals of a circuit while that circuit is operating.

When referring to a TAP controller, a register that controls the operation of the TAP.

See Instruction Register.

The name of the standards group which created the IEEE 1149.1 specification.

Memory organization where the least significant byte of a word is at a lower address than the most significant byte. See also Big-endian.

Hardware that controls caches and access permissions to blocks of memory, and translates virtual to physical addresses.

Multi-processor EmbeddedICE interface.

Abbreviation of System Reset. The electronic signal which causes the target system other than the TAP controller to be reset. This signal is known as nSYSRST in some other manuals. See also nTRST.

Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some other manuals. See also nSRST.

A signal that may be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a “wired-AND” signal.

The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit, and the register bank. It excludes optional coprocessors, caches, and the memory management unit.

Contains some information about the current program and some information about the current processor. Often, therefore, also referred to as Processor Status Register.

Is also referred to as Current PSR (CPSR), to emphasize the distinction between it and the Saved PSR (SPSR). The SPSR holds the value the PSR had when the current function was called, and which will be restored when control is returned.

Changing the address of physical memory or devices after the application has started executing. This is typically done to allow RAM to replace ROM once the initialization has been done.

RDI is an open ARM standard procedural interface between a debugger and the debug agent. The widest possible adoption of this standard is encouraged.

Returned TCK. The signal which enables Adaptive Clocking.

Real Time Operating System.

A group of one or more registers from one or more TAP controllers connected between TDI and TDO, through which test data is shifted.

A mechanism whereby the target communicates I/O requests made in the application code to the host system, rather than attempting to support the I/O itself.

Software Interrupt. An instruction that causes the processor to call a programer-specified subroutine. Used by ARM to handle semihosting.

Logic on a device, which allows access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1.

The actual processor (real silicon or simulated) on which the application program is running.

The electronic clock signal, which times data on the TAP data lines TMS, TDI, and TDO.

The electronic signal input to a TAP controller from the data source (upstream). Usually this is seen connecting the Multi-ICE Interface Unit to the first TAP controller.

The electronic signal output from a TAP controller to the data sink (downstream). Usually this is seen connecting the last TAP controller to the Multi-ICE Interface Unit.

The port used to access a device's TAP Controller. Comprises TCK, TMS, TDI, TDO, and nTRST (optional).

A type of logic design in which two bipolar transistors drive the logic output to one or zero. LSI and VLSI logic often used TTL with HIGH logic level approaching +5V and LOW approaching 0V.

A location within the image that will be monitored and cause execution to stop when it changes.

A 32-bit unit of information. Contents are taken as being an unsigned integer, unless otherwise stated.