1.6.1 Maximum Current Limits May Be Higher Than Specified In the Data Sheet

The IDD and IPD limits do not match the data sheet.

All IDD maximum limits will equal 2.8 times the values listed in the data sheet.

The IPD values, shown in bold in the table below, reflect the updated silicon maximum limits.

Table 1-2. 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended)
PIC18F66K80 (Industrial/Extended)Standard Operating Conditions (unless otherwise stated)
Param No.DeviceTyp.Max.UnitsConditions
Power-Down Current (IPD)(1)
PIC18LFXXK800.0087μA-40°C

VDD = 1.8V(4)

(Sleep mode)

Regulator Disabled

0.0137μA+25°C
0.0359μA+60°C
0.21810μA+85°C
312μA+125°C
PIC18LFXXK800.0148μA-40°C

VDD = 3.3V(4)

(Sleep mode)

Regulator Disabled

0.0348μA+25°C
0.0929μA+60°C
0.31210μA+85°C
416μA+125°C
PIC18FXXK800.29μA-40°C

VDD = 3.3V

(Sleep mode)

Regulator Enabled

0.239μA+25°C
0.3210μA+60°C
0.5111μA+85°C
518μA+125°C
PIC18FXXK800.2210μA-40°C

VDD = 5.5V(5)

(Sleep mode)

Regulator Enabled

0.2410μA+25°C
0.3411μA+60°C
0.5412μA+85°C
520μA+125°C
Note:
  1. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the device in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, SOSC oscillator, BOR, etc.).

  2. The supply current is mainly a function of operating voltage, frequency, and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.

    The test conditions for all IDD measurements in active operation mode are:
    • OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
    • MCLR = VDD; WDT enabled/disabled as specified.
  3. Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.
  4. For LF devices, RETEN = 1.
  5. For F devices, SRETEN = 1 and RETEN = 0.

Work around

None.

Affected Silicon Revisions

A2A3A4A6A7
X