Silicon Issue Summary
| Module | Feature | Item No. | Issue Summary | Affected Revisions | ||||
|---|---|---|---|---|---|---|---|---|
| A2 | A3 | A4 | A6 | A7 | ||||
| Analog-to-Digital Converter (ADC) | ADC Performance | 1.1.1 | The 12-Bit ADC Performance is Outside the Data Sheet's Specifications | X | X | X | X | X |
| Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) | Synchronous Transmit | 1.2.1 | Transmitted Data May Become Corrupted in Synchronous Transmit Mode | X | ||||
| Receive Interrupt | 1.2.2 | Unintended Double
Execution of the CALL
Instruction | X | X | X | X | X | |
| Enhanced Capture Compare PWM (ECCP) | Auto-Shutdown | 1.3.1 | The PWM's Tri-State Setting of the Auto-Shutdown Feature Will Not Drive the Pin to Tri-State | X | X | X | X | X |
| Enhanced Controller Area Network (ECAN) | CAN Clock Source Selection | 1.4.1 | The CLKSEL Bit in the CIOCON Register is Modifiable While the ECAN Module is Active | X | ||||
| Enhanced Window Address (EWIN) | 1.4.2 | The EWIN Feature Will Not Move the BnCON[0...5] Registers Into the Access Window of RAM | X | |||||
| Disable/Sleep Mode | 1.4.3 | Disable/Sleep Mode Reverts CANTX Control to TRISx/LATx Instead of Going to Recessive State | X | X | X | X | X | |
| CLKSEL Bit | 1.4.4 | Setting the CLKSEL Bit of CIOCON Can Occasionally Lead to Missed Incoming CAN Messages | X | X | X | X | X | |
| Ultra Low-Power Sleep | Sleep Entry | 1.5.1 | Entering Ultra
Low-Power Sleep Mode By Setting
RETEN =
0 and
SRETEN =
1Will Cause the Device to Become
Unprogrammable Through ICSP™ | X | ||||
| Electrical Specifications | IPD/IDD Maximum Limits | 1.6.1 | Maximum Current Limits May Be Higher Than Specified In the Data Sheet | X | ||||
| Resets | BOR Enable/Disable | 1.7.1 | An Unexpected Reset May Occur if the BOR Module is Disabled and Then Re-Enabled When the HLVD Module is Not Enabled | X | X | X | X | X |
| Master Clear Enable | 1.7.2 | The
MCLR Pin Will Not Be
Readable When MCLRE = 0 for All
28-Pin Variants | X | X | X | X | X | |
| Timer1/3 | Gated Enable | 1.8.1 | Timer1/3 Gate Control Will Not Function Up to the Speed of FOSC When TxCON is Set to the System Clock | X | X | |||
| Interrupt | 1.8.2 | Unexpected Interrupt Flag Generation May Occur in Asynchronous External Input Mode | X | X | X | X | X | |
| Primary Oscillator | XT Mode | 1.9.1 | XT Primary Oscillator Mode Does Not Reliably Function When the Driving Crystals are Above 3 MHz | X | X | X | ||
| Instruction Set | PUSHL Instruction | 1.10.1 | The
PUSHL instruction incorrectly
executes | X | X | X | X | X |
|
Note: Only those issues indicated in the last column
apply to the current silicon revision.
| ||||||||