1.1.1 The 12-Bit ADC Performance is Outside the Data Sheet's Specifications
The 12-bit ADC performance is outside the data sheet's ADC specifications. When used as a 12-bit
ADC, the possible issues are:
- High offset error:
- up to a maximum of ±25 LSb at 25°C
- up to a maximum of ±30 LSb at -40°C, 85°C, and 125°C
- High DNL error:
- up to a maximum of +6.0/-4.0 LSb
- Multiple missing codes:
- up to a maximum of 20 missing codes
Reduced bit resolution specifications can be derived by dividing, as appropriate. For instance, 10-bit guidance is obtained by dividing the parameters in the table below by four.
| Standard Operating Conditions (unless otherwise stated) | |||||||
|---|---|---|---|---|---|---|---|
| Param No. | Sym. | Characteristics | Min. | Typ† | Max. | Units | Conditions |
| A01 | NR | Resolution | — | — | 12 | bit | ΔVREF ≥ 5.0V |
| A02 | EIL | Integral Linearity Error | — | — | ±10 | LSb | ΔVREF ≥ 5.0V |
| A04 | EDL | Differential Linearity Error | — | — | +6.0/-4.0 | LSb | ΔVREF ≥ 5.0V |
| A06 | EOFF | Offset Error |
— — |
— — |
±25 ±30 |
LSb LSb |
ΔVREF ≥ 5.0V, 25°C ΔVREF ≥ 5.0V, -40°C, 85°C, 125°C |
| A07 | EGN | Gain Error | — | — | ±15 | LSb | ΔVREF ≥ 5.0V |
| A10 | — | Monotonicity(1) | — | — | — | — | VSS ≤ VAIN ≤ VREF |
| A20 | ΔVREF | Reference Voltage Range (VREFH - VREFL) | 3 | — | AVDD - AVSS | V | |
| A21 | VREFH | Reference Voltage High | AVSS + 3.0V | — | AVDD + 0.3V | V | |
| A22 | VREFL | Reference Voltage Low | AVSS - 0.3V | — | AVDD - 3.0V | V | |
| A25 | VAIN | Analog Input Voltage | VREFL | — | VREFH | V | |
|
Note:
| |||||||
Work around
Calibrate for offset in Single-Ended mode by connecting a positive ADC input to ground and taking the reading. This will be the offset of the device and can be used to compensate for the subsequent readings on the actual inputs.
Affected Silicon Revisions
| A2 | A3 | A4 | A6 | A7 | |||
| X | X | X | X | X |
