1.1.1 The FSCM May Fail to Trigger with 4x PLL Enabled
The Fail-Safe Clock Monitor may fail to trigger with the loss of the external clock signal when the 4x PLL is enabled. This includes all external clock modes: LP, XT, HS, ECL, ECM, and ECH.
Work around
None.
Affected Silicon Revisions
| A1 | A2 | A3 | A4 | ||||
| X |
