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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
2
CPU and Interconnect
2.3
Bus Matrix (MATRIX)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
ARM926EJ-S Processor
2.2
Debug and Test
2.3
Bus Matrix (MATRIX)
2.3.1
Description
2.3.2
Embedded Characteristics
2.3.3
Memory Mapping
2.3.4
Special Bus Granting Techniques
2.3.5
No Default Host
2.3.6
Last Access Host
2.3.7
Fixed Default Host
2.3.8
Arbitration
2.3.9
Register Write Protection
2.3.10
Register Summary
2.4
DMA Controller (XDMAC)
2.5
Boot Strategies
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
2.3 Bus Matrix (MATRIX)
