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4.3.2 Embedded Characteristics
- Controls the Interrupt Lines (nIRQ and nFIQ) of an Arm Processor
- 50 Individually Maskable and Vectored
Interrupt Sources
- Source 0 is reserved for the fast interrupt input (FIQ)
- Source 1 is reserved for system peripheral
interrupts
- Source 2 to Source 49 control up to
126 embedded
peripheral interrupts or external interrupts
- Programmable edge-triggered or level-sensitive internal
sources
- Programmable rising/falling edge-triggered or high/low
level-sensitive external sources
- 8-level Priority Controller
- Drives the normal interrupt of the processor
- Handles priority of the interrupt sources 1 to 49
- Higher priority interrupts can be served during service of lower priority interrupt
- Vectoring
- Optimizes interrupt service routine branch and execution
- One 32-bit vector register for all interrupt sources
- Interrupt vector register reads the corresponding current interrupt vector or the current interrupt number
- Protect Mode
- Easy debugging by preventing automatic operations when protect models are enabled
- Fast Forcing
- Permits redirecting any normal interrupt source to the fast interrupt of the processor
- General Interrupt Mask
- Provides processor synchronization on events without triggering an interrupt
- Register Write Protection