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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
3
Memories
3.8
OTP Memory Controller (OTPC)
3.8.5
Functional Description
3.8.5.3
User Area
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
SDRAM Controller (SDRAMC)
3.8
OTP Memory Controller (OTPC)
3.8.1
Description
3.8.2
Embedded Characteristics
3.8.3
Block Diagram
3.8.4
Product Dependencies
3.8.5
Functional Description
3.8.5.1
Bus Interfaces
3.8.5.2
OTP Memory Partitioning
3.8.5.3
User Area
3.8.5.3.1
Area Configuration and Control
3.8.5.3.2
Area Mapping
3.8.5.3.3
Packet Definition
3.8.5.3.4
Init
3.8.5.3.5
Read Access
3.8.5.3.6
Write (Program) Considerations
3.8.5.3.7
Write (Program) Access
3.8.5.3.8
Fixing Corruption
3.8.5.3.9
“Software” Protections
3.8.5.3.10
“Hardware” Protections
3.8.5.4
OTP Emulation Mode
3.8.5.5
Interrupts
3.8.5.6
Register Write Protection
3.8.6
Register Summary
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.8.5.3 User Area
