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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
2
CPU and Interconnect
2.5
Boot Strategies
2.5.2
Secure Boot Strategy
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
ARM926EJ-S Processor
2.2
Debug and Test
2.3
Bus Matrix (MATRIX)
2.4
DMA Controller (XDMAC)
2.5
Boot Strategies
2.5.1
Standard Boot Strategy
2.5.2
Secure Boot Strategy
2.5.2.1
Description
2.5.2.2
Secure Boot Configuration
2.5.2.3
Secure Boot Configuration Packet
2.5.2.4
Valid Code Detection in Secure Boot Mode
2.5.2.5
Encryption, Decryption and Authentication
2.5.2.6
Secure Monitor
2.5.2.7
Secure Boot Mode Recommendations
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
2.5.2 Secure Boot Strategy
