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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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SAM9X60
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9
USB Subsystem
9.2
USB Device High Speed Port (UDPHS)
9.2.6
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
9.1
Overview
9.2
USB Device High Speed Port (UDPHS)
9.2.1
Description
9.2.2
Embedded Characteristics
9.2.3
Block Diagram
9.2.4
Typical Connection
9.2.5
Product Dependencies
9.2.6
Functional Description
9.2.6.1
UTMI Transceivers Sharing
9.2.6.2
USB V2.0 High Speed Device Port Introduction
9.2.6.3
USB V2.0 High Speed Transfer Types
9.2.6.4
USB Transfer Event Definitions
9.2.6.5
USB V2.0 High Speed BUS Transactions
9.2.6.6
Endpoint Configuration
9.2.6.7
DPRAM Management
9.2.6.8
Transfer With DMA
9.2.6.9
Transfer Without DMA
9.2.6.10
Handling Transactions with USB V2.0 Device Peripheral
9.2.6.11
Speed Identification
9.2.6.12
USB V2.0 High Speed Global Interrupt
9.2.6.13
Endpoint Interrupts
9.2.6.14
Power Modes
9.2.6.15
Test Mode
9.2
Register Summary
9.3
USB Host High Speed Port (UHPHS)
9.4
Analog-to-Digital Controller (ADC)
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
9.2.6 Functional Description
