26.3.6 Interrupts

Table 26-2. Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 Slave TWI Slave interrupt
0x02 Master TWI Master interrupt
When an interrupt condition occurs, the corresponding interrupt flag is set in the Master register (TWI.MSTATUS) or Slave Status register (TWI.SSTATUS).
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed together into one combined interrupt request to the interrupt controller. The user must read the peripheral's INTFLAGS register to determine which of the interrupt conditions are present.