30.3.2.3 Conversion Timing

A normal conversion takes 13 CLK_ADC cycles. The actual sample-and-hold takes place two CLK_ADC cycles after the start of a conversion. Start of conversion is initiated by writing a ‘1’ to the STCONV bit in ADC.COMMAND. When a conversion is complete, the result is available in the Result register (ADC.RES), and the Result Ready interrupt flag is set (RESRDY in ADC.INTFLAG). The interrupt flag will be cleared when the result is read from the Result registers, or by writing a ‘1’ to the RESRDY bit in ADC.INTFLAG.

Both sampling time and sampling length can be adjusted using the Sample Delay bit field in Control D (ADC.CTRLD) and sampling the Sample Length bit field in the Sample Control register (ADC.SAMPCTRL). Both of these control the ADC sampling time in a number of CLK_ADC cycles. This allows sampling high-impedance sources without relaxing conversion speed. See the register description for further information. Total sampling time is given by:

$\mathrm{SampleTime}=\frac{(2+\text{SAMPDLY}+\text{SAMPLEN})}{f_{\text{CLK\_ADC}}}$

In Free-Running mode, a new conversion will be started immediately after the conversion completes, while the STCONV bit is ‘1’. The sampling rate R_S in free-running mode is calculated by:

$R_{\text{S}}=\frac{f_{\text{CLK\_ADC}}}{(13+\text{SAMPDLY}+\text{SAMPLEN})}$